Low power dynamic comparator for 4 — bit Flash ADC

Abstract

Among all the ADC architectures, Flash ADCs are the most preferred ones. High speed operation is the main reason for selecting Flash ADC. Applications which require high speed conversion in mixed mode signal processing needs Flash ADC. In order to have high speed Flash ADC, the design of comparators is the main task. Since comparators in Flash ADC are power hungry components, we should design each compactor in such a way that overall power consumption should be less. Here we have designed a dynamic comparator consuming low power of 0.169uW. Then we have implemented encoder block using 2:1 MUX. Using these components we have implemented 4-bit Flash ADC which is having power dissipation of 7.2394mW and delay of 29.792ns. The design is implemented in Mentor Graphics tool using 180nm Technology.