Abstract
As VLSI technology gaining more popular power consumption and high speed are the major constraints. In Mixed signal ICâs it is a necessity of minimum power dissipation in order to limit energy in a reasonable size batteries. Analog to digital converter is the key to mixed signal ICâs. Analog to digital converters are the basic component in modern communications, handheld wireless computers and signal processing systems. In this paper most preferred and high speed flash ADC using CMOS latch comparator is presented. Normally Flash Adc takes large number of comparators as size of ADC increases. In this comparator count will be decreased by using multiplexing of reference signal and reduce power dissipation using dynamic latch comparator. This design is simulated and results are presented. The presented flash ADC consumes 212.47uwatts power at a frequency of 1000 MHz with an operating voltage of 1.8v.
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