Abstract
A new 6-bit flash ADC structure is proposed in this paper. The typical 63-to-6 encoder in a traditional flash ADC is replaced by a 7-to-3 LSBs encoder and an 8-to-3 MSBs encoder. The complexity of the physical circuit of this new encoder is lowered greatly. Hence both power dissipation and area consumption are minimized. Besides, to enhance the bubble error tolerance, a new proposed encoding scheme is applied to the LSBs encoder. Traditionally, a encoder that can efficiently remove the bubble errors always suffers the problem of long latency. This problem becomes a bottleneck in the design of high speed flash ADC nowadays. In this proposed 6-bit flash ADC, the trade-off between bubble tolerance and latency is optimized. The proposed encoding scheme can provide very high bubble error tolerance with ultra short latency. It is proved that the delay of the encoder is only 3 gate-levels. Simulation results demonstrate the benefits introduced above. It is seen that this new flash ADC offers an excellent choice for modern high speed ADC application.
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