Low-Power Code Memory Integrity Verification Using Background Cyclic Redundancy Check Calculator Based on Binary Code Inversion Method

Abstract

The integrity verification of on-chip flash memory data as code memory is becoming important in microcontroller-based applications such as automotive systems. On-the-fly memory fail-detection requires a fast detection method in the seamless background mode without any interruption of CPU operation and low-power flash access hardware to provide safety-conscious execution of the user-programmed firmware during system operations. In this paper, newly-designed read-path architecture based on the binary inversion techniques is proposed for on-chip flash-embedded microcontrollers. The proposed binary inversion method also enables fail-safe, low-power memory access with zero hardware overhead by embedding the scramble flags on the cyclic redundancy check (CRC) protection code. Time-multiplexed CRC calculation for bit-inversion binary code is automatically executed with the silent background mode during CPU idle time without any CPU wait cost. The implementation result shows that the de-inversion procedure could be achieved with just an additional 1,024 bits CRC data in the case of 64 sectors for 4 KB flash memory by reducing 75% of the area of the previous work. The code memory integrity verification time in the seamless background mode is about 30% of the conventional foreground method. The total average current during the code execution for DhrystoneTM benchmark uses just 15% of the basement.