Terminated Staircase Codes for NAND Flash Memories

Abstract

In this paper, we propose novel terminated staircase codes for NAND flash memories. Specifically, we design a rate 0.89 staircase code whose component code is a Bose–Chaudhuri–Hocquenghem (BCH) code, for flash memories with page size of 16K bytes. Different from most conventional unterminated staircase codes, we propose a novel coding structure by performing cyclic redundancy check (CRC) encoding and decoding on each component codeword including information bits and parity bits. The CRC bits are protected by both row and column codewords. Furthermore, a novel iterative bit flipping algorithm is developed to solve stall patterns and lower the error floor. Based on our design, we perform an improved analysis on the error floor. We prove and show that our proposed decoding algorithm can solve more stall patterns which leads to a lower error floor compared with conventional staircase codes. Numerical results show that our terminated staircase codes outperform the stand-alone BCH codes and the conventional staircase codes.