On Relative Performances and Decoding of CRC Concatenated Polar Codes with Different Lists for Solid-State Drives

Abstract

The storage capacity and cost-per-bit of solid-state drives (SSDs) have improved gradually in recent years, which have driven to the extensive acceptance in data storage of modern computing systems. SSDs convey greater read and write performance, enhancement in random-access input/output (I/O) operations, and resistance to physical shock, while form factor and static power requirement are not as much of magnetic hard disk drives (HDDs). Though HDDs are progressively replaced by SSDs as a primary data storage, error correction is still severe to SSDs as NAND flash memories have worsening reliability which can diminish the life span of the flash storage devices. Presently, popular error control codes show inadequate error correction ability or poor error floor, and the growing storage density of NAND flash memory cells exhibits more data errors. All of these stimulate probing for finest channel coding to recover NAND flash reliability. Polar codes are favorable for SSDs as they are theoretically verified optimal codes with good error floor behavior. With the low computational complexity and the high error correction competency, cyclic redundancy check (CRC) concatenated polar code with list decoding can beat existing error correction codes in data communication applications. Hence, it also steered to implement in flash storage devices. In this paper, CRC concatenated polar codes with different list sizes for SSDs are designed and error correction performances are evaluated in C/C++ environment. Evaluated outcomes illustrate the decoding performance achieving preferred error floor behavior for error correction in flash storage devices. While the outcomes display that concatenated polar codes with list decoding are favorable for SSDs, some open problems are remained there for further investigations.