Safe memory read-path using silent CRC calculation of binary bit-inversion for low-power fast ROM integrity verifcation

Abstract

The integrity verifcation of on-chip fash memory data as code memory is becoming important in microcontroller-based applications. On-the-fy memory fail-detection without any interruption of CPU operation requires a fast detection method and low-power fash access hardware to provide safety-conscious execution of the user-programmed frmware during system operations. In this paper, newly-designed read-path architecture for an on-chip fash-embedded microcontroller is proposed in order to provide a memory scrambling method that enables fail-safe low-power memory access with zero hardware overhead by embedding the scramble fags on the CRC protection code. Time-multiplexed CRC calculation for bit-inversion binary code is automatically executed with the silent background mode during CPU idle time without any CPU wait cost. Te implementation result shows the de-inversion procedure could be achieved with only additional 1024 bits CRC data in case of 64 sectors for 4 KB fash memory by reducing 75% area of the previous work.