Low frequency noise behaviors in the partially depleted silicon-on-insulator device

Abstract

Low frequency noise in the partially depleted silicon-on-insulator (SOI) NMOS device is investigated in this paper. The experimental results show low frequency noise behaviors are in good consistence with classical noise model. Based on McWhorter model, the low frequency noise in the SOI device results from the exchange of carriers between channel and oxide. The densities of trapped charges in the front gate oxide and buried oxide are extracted. Due to the difference between manufacture processes, the extracted density of trapped charges in the buried oxide (Nt=8×1017 eV-1·cm-3) is larger than that in the gate oxide (Nt=2.767×1017 eV-1·cm-3), and the result is in good agreement with testing result of transfer characteristics in part 2. Based on the charge tunneling mechanism, the spatial distribution of trapped charges in the gate oxide and buried oxide are extracted by using the tunneling attenuation coefficient (λ=0.1 nm for SiO2) and time constant (τ0=10-10 s), and the result also proves that the trap in buried oxide is larger than that in gate oxide. In addition, the influence of channel length on the low frequency noise in the SOI device is discussed. The variations of normalized channel current noise power spectral density with channel length are investigated at four frequencies(10 Hz, 25 Hz, 50 Hz, and 100 Hz). The experimental results show that the normalized noise power spectral density decreases linearly with the increase of channel length, which indicates the low frequency noise of SOI device is mainly caused by the flicker noise in the channel, and the contribution of source/drain contact and parasitic resistances could be ignored. Finally, the dependences of back gate voltage on the front gate threshold voltage, front channel current and front channel noise are discussed by considering the charge coupling effect. The experimental results show the measured channel current and channel noise with applying front gate voltage and back gate voltage simultaneously are larger than those with applying the front gate voltage and back gate voltage separately.