Abstract
The development of cost-effective, void- and lead-free high-power die attach for automotive power modules has been a major challenge for the last decades. Particularly voids at the die attach have the potential of reducing the lifetime of the interconnection between the die and the direct copper bonded (DCB) substrate demonstrably, caused by overheating of the die [1]. This study evaluates a method to determine the influence of the void position and size on the local thermal resistance of the solder interconnection. The formular of the local thermal resistance generated by using FEM simulation shows, that the permitted local maximum void size depends on the position of the void. The defined correlation factor reduces the individual void areas according to their position and thus the permitted thermal resistance is not exceeded.
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