Leakage Power Analysis of Domino XOR Gate

A K Pandey,R K Nagaria,R A Mishra

doi:10.1155/2013/271316

Abstract

Two new XOR gates are proposed. First proposed circuits adopt hybrid transistor topology in the pull-down network with all transistors being low threshold voltages. A second proposed circuit adopts hybrid topology with dual threshold voltage transistors. Simulation parameters are measured at 25°C and 110°C. First proposed circuit reduces leakage power consumption up to 50% at 25°C and 58% at 110°C as compared to standard N-type domino XOR gate. It also reduces active mode power consumption by 14% as compared to standard N-type domino XOR gate. Similarly, second proposed circuit reduces leakage power consumption up to 73% at 25°C and 90% at 110°C as compared to standard N-type domino XOR gate. It also reduces active mode power consumption by 39% as compared to standard N-type domino XOR gate.

Highlights

CMOS XOR gates are the fundamental units, it is used in many VLSI applications such as adders and microprocessors
Due to its superior performance and low power consumption, domino XOR is being used in many VLSI applications
Comparison of normalized subthreshold leakage current and gate oxide leakage current produced by low-VVtt transistor and high-VVtt transistor in dual VVtt CMOS technology as shown in Table 1 [14]

Summary

Introduction

CMOS XOR gates are the fundamental units, it is used in many VLSI applications such as adders and microprocessors. Comparison of normalized subthreshold leakage current and gate oxide leakage current produced by low-VVtt transistor and high-VVtt transistor in dual VVtt CMOS technology as shown in Table 1 [14]. T 1: Normalized subthreshold and gate oxide leakage currents of the low-VVtt and high-VVtt transistors at two different temperatures [14]. E gate oxide leakage current produced by a low-VVtt nMOS transistor is 34 times and 30 times higher than ttrhaengsaistteoor xaitd1e1l0e∘aCkaagnedc2u5r∘rCen. t preogdautceeodxbidyealeloakwa-gVeVttcpuMrreOnSt for pMOS device is lower as compared to an nMOS device with the same width and length with different TTox and the same voltage difference across the gate insulator. F 4: Comparison of subthreshold and gate oxide leakage current of low-VVtt and high-VVtt transistors at two different temperatures. F 7: Hybrid domino XOR gate with low threshold voltage transistors (DXHL)

Proposed XOR Structures

Simulation Results

Conclusion