Abstract
A 64-bit low threshold voltage conditional carry adder using complementary pass-transistor logic for low-voltage and high-speed application was presented. The improved conditional sum addition rule can reduce the number of internal nodes and multiplexers in the adder design. And reducing the threshold voltage increases the speed of operation. Thus, a low threshold voltage design is favourable for implementing low-voltage, high-speed arithmetic systems. The performances of such circuits are compared with that of normal and zero threshold voltage schemes; the proposed circuit gets the lowest power-delay product and energy-delay product from 1.0V to 2.5V. The circuit is demonstrated to balance between power consumption and performance effectively.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
