Layout aid for the design of VLSI circuits

Abstract

VLSI (very large scale integration) circuits are the most complex chips yet developed, typically having over 50 000 transistors. Some examples are a 16 kbit static RAM chip or a 16 bit microprocessor chip. The complexity of these chips necessitates the invention of new techniques in order to reduce production costs and design time. The design cycle of an IC (integrated circuit) consists of a series of complex tasks often requiring more than a year to complete. As ICs grow in complexity, the cycle time increases and could potentially become too lengthy to be realistic. One of the most time consuming tasks in the design cycle is laying out a circuit. This paper describes a new layout aid that will significantly reduce the layout time. In this new layout aid, a designer is required to digitize an approximate layout, fully routed but loosely placed. From this approximate layout, two graphs are created, one representing the relative vertical position of each circuit element in the loose sketch, and the other representing their relative horizontal position. In the graphs, modes indicate the coordinate locations and branches indicate minimum spacing requirements due to design rules. An optimization technique, namely the longest path algorithm, is invoked to compact the circuit. In the original layout, design rule violations may be overlooked, which will prevent the longest path algorithm from converging. A method is devised to resolve this problem. Results of empirical testing of the new layout aid are reported.