(Invited) Compliance-Free Pulse Forming of Filamentary RRAM

Abstract

Despite the overwhelming effort to improve the efficacy of resistive random access memory (RRAM), the underlying physics governing RRAM operation have proven elusive. Consequently, substantial effort has been spent to empirically develop transition metal oxide (filamentary) RRAM structures which exhibit reasonable behavior [1,2]. A survey of the recent literature almost universally indicates that the remaining glaring issues center around device variability as well as endurance. Perhaps the only consensus in the RRAM community is that these issues are linked to the forming process [2,3]. The forming process is an initial conditioning step in which voltage is applied across the dielectric stack to form, or break-down, the oxide via the formation of a resistive filament [2,3]. The forming process is thought to greatly determine the subsequent behavior of the device [2,3]. Thus, the vast majority of this presentation will detail our recent efforts to bring the forming process under control and the resulting improvements in RRAM viability in HfO2-based devices. The vast majority of efforts to control the forming process all involve the inclusion of an additional series resistor element to limit the current that flows through the RRAM during forming (compliance). Our efforts show that even the most careful series resistor implementation still invokes a serious forming variability due to the unavoidable parasitic capacitance [4]. These parasitics introduce a current overshoot which greatly alters the ability to terminate forming (i.e. a large current continues to flow through the filament for some uncontrollable time before the compliance element can clamp) [4]. This introduces a relatively large uncertainty in the forming energy ((forming voltage) x (current) x (time)) and consequent variability in the filament [5]. This pitfall can be avoided by removing all current compliance elements, and their associated parasitics, and utilizing ultrashort voltage pulses to induce forming [5,6]. In this approach, the forming process can occur uncontrolled at any point in time during the voltage pulse. However, utilization of the ultrashort pulse width minimizes the timing uncertainty and bring the forming energy under control [5]. One can, of course, invoke multi-pulse approaches to further tune the forming energy to the specific RRAM device stack [5]. Using this approach, we show for nominally identical RRAM devices, varying the forming energy using ~100 ps pulses can greatly alter the variability as measured via the endurance window [5]. In extreme cases, we show that a change in forming energy can effectively open up an endurance window in a device which was unusable using more traditional forming methods [5]. In addition, we show (figure 1) further improvement in endurance when applying multiple pulse forming schemes to “tune” the forming energy to the desired value and consequent endurance [5]. In summary, we describe a new compliance-free RRAM forming technique that greatly enhances the energy control of the forming process and improves the device endurance characteristics proportionately. [1] Y. Shimeng, et al., IEDM, pp. 26.1.1 (2012) [2] B. Butcher, et al., IIRW, pp. 146 (2011) [3] A. Kalantarian, IRPS, pp. 6C.4.1 (2012) [4] P. Shrestha, et al., IIRW, pp. 55 (2013) [5] P. Shrestha, et al., IRPS, pp. MY.10.1 (2014) [6] P. Shrestha, et al., VLSI-TSA, pp. TR82 (2014) Figure 1