(Invited) Challenges and Opportunities for Selective Area Processing in High Volume Manufacturing (HVM)

Abstract

In the recent years scaling approach to Moore’s law has slowed, there is longing for innovations in processes, design, tools, and materials. Selective deposition is one of them which has been used in various forms, most communally, metals on metals in the semiconductor industry. More advanced forms of selective area process such as metals on dielectrics, dielectrics on metals and dielectrics on dielectrics are making some progress at the industrial level for integration at HVM level. Since it has the potential to reduce the number of lithographic and etch steps in the manufacturing flow, it has been pursued actively at academic as well as at an industrial level. In this talk, we will explore the selective processing applications which are driving the driving the semiconductor industry to look beyond conventional top-down processing. Applications where selective deposition are needed will be discussed. We will then look at the bottlenecks which needs to be addressed for selective processing technique to become a high volume manufacturable (HVM) process. The challenges and opportunities for HVM will be presented with an emphasis on the need for low defectivity, low cost, high throughput, repeatable, processes that can be applied across a 300 mm wafer without the loss of unit film properties. We will discuss some approaches that Lam Research is taking to meet these requirements, and also where innovation is still needed. Through this presentation, we hope to bring synergy and accelerate innovation in HVM-compatible selective processing.