Selective Electroless Metal Deposition for Integrated Circuit Fabrication

Abstract

Selective electroless metal deposition process was studied for its applications in integrated circuit fabrication. Compared to selective metal deposition by CVD process, such as the selective tungsten deposition process, the selective electroless deposition process is more attractive due to its simplicity as well as process flexibility. A variety of material such as Ni, Co, Pd, and Cu were studied for contact filling, via filling, and for conductor patterns. These materials were selectively deposited on a variety of surfaces such as silicon, silicide, Al‐Si, through patterned CVD silicon dioxide, CVD silicon oxynitride, and photoresist. Although this process is still in its early stage of development, very promising results have already been achieved. The experimental conditions and results for selectively filled contact holes, via holes, and conductor patterns are described using actual examples.