Interface studies on high-k/GaAs MOS capacitors by deep level transient spectroscopy

Abstract

An experimental analysis has been performed in high-k/GaAs MOS devices to investigate the slow and fast interface traps (Dit) using high frequency capacitance-voltage and deep level transient spectroscopic (DLTS) measurements. Prior to deposition of high-k gate dielectric, an ultrathin layer of ZnO was deposited on GaAs by metalorganic chemical vapor deposition. The number of slow interface traps was found to be 2.80 × 1011 cm−2, whereas the fast interface trap density was measured to be 1.80 × 1011 eV−1 cm−2. The activation energy, capture cross section, and concentration of majority carrier traps were measured to be 0.30 eV, 5.70 × 10−19 cm2, and 4.93 × 1015 cm−3, respectively. Combining conventional DLTS with insufficient-filling, the trap location was found to be at 0.14 eV. Therefore, the traps are not exactly at the interface of GaAs and high-k but in the GaAs surfaces very close to the interfaces. According to the trap energy level position, Dit was found to be 5.3 × 1011 eV−1 cm−2. The leakage current is found to reduce in ZnO passivated devices due to an increase in valance band offset by 0.49 eV. Such an improvement is due to a higher surface potential resulting from the wide bandgap of ZnO.