Metal-Oxide-Semiconductor Devices on GaAs with High-k Dielectric and MOCVD Grown ZnO Interface Passivation Layer

Abstract

We report fabrication of GaAs metal-oxide- semiconductor devices with an unpinned interface for improved electrical performance. An ultrathin (~1.8 nm) interface passivation layer (IPL) of ZnO, on GaAs, grown by metal organic chemical vapor deposition prior to the high-k deposition, is proposed to solve the issue of interface pinning. X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy results show that an ultra thin layer of ZnO IPL can effectively suppress the oxides formation and minimize the Fermi level pinning at the interface between the GaAs and TiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . The advantage of GaAs passivation with MOCVD grown ZnO is demonstrated with very small hysteresis, 2 - 4% frequency dispersion per decade at accumulation capacitance, and a midgap interface trap density as low as 2.5×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> determined by full conductance method. The capacitance-voltage (C-V), current density-voltage (J-V) characteristics and charge trapping behavior of the films under constant voltage stressing exhibit an excellent interface quality and high dielectric reliability making the device suitable for advanced complementary metal-oxide-semiconductor (CMOS) and microelectronic applications.