Increasing the Accuracy of Approximate Adders with Very Low Extra Complexity

Abstract

Approximate computing has gained great interest in the very large scale integration (VLSI) circuits design field. Approximate computing, which makes use of the inherent error-resilient nature of some systems, can significantly reduce the energy consumption, area overhead, and critical path delay at the cost of negligible system performance degradation. Approximate adders are one of the most popular approximate arithmetical units. In this paper, four types of enhanced approximate adders are proposed. Compared with their original counterparts, these enhanced approximate adders can achieve much higher computational precisions while only demanding a little more energy and area. For instance, compared with the original approximate carry skip adder (ACSA), the proposed enhanced ACSA (EACSA) can halve the error rate and reduce about 50% mean absolute error, 50% mean square error, and 48.6% energy-delay-error rate product, while the EACSA merely brings about 2.1 %, 2.2%, and 1.9 % increments in the area, power, and energy, respectively, when implemented using a commercial 90-nm CMOS technology. Moreover, all the enhanced approximate adders can maintain the same critical path delay as their original counterparts.