An Approximate Adder with Reduced Error and Optimized Design Metrics

Abstract

We present a new approximate adder with reduced error and optimized design metrics. The proposed approximate adder is derived by modifying an existing approximate adder HERLOA and is called modified HERLOA or M-HERLOA in short. We considered a systematic modification of HERLOA to derive an optimum M-HERLOA for a digital image processing application. We calculated popular error parameters such as mean absolute error (also called mean error distance) and root mean square error of the approximate adders. We estimated the design metrics of accurate and approximate adders based on FPGA and ASIC (standard cell based) implementations. We compare the performance of accurate adder and approximate adders for an image processing application by estimating the peak signal to noise ratio and structural similarity index metric. We find that the proposed M-HERLOA reconstructs a digital image that is similar to the image reconstructed using the accurate adder. This is achieved with M-HERLOA simultaneously enabling following optimizations in design metrics compared to the accurate adder for a 32 bit addition: (i) 9.5% reduction in minimum clock period, 9.1% reduction in total on-chip power consumption, and 7 LUTs and 18 flip-flops less for a FPGA implementation, and (ii) 18% reduction in critical path delay, 26.7% reduction in average power dissipation, and 23.1% reduction in silicon area for an ASIC type implementation.