Energy efficient high-performance approximate adders for imprecision-tolerant signal processing applications

Abstract

The trade-off between Delay and Power consumption has become a major concern as process technology reached less than 10 nm proximity in the modern Very Large-Scale Integration (VLSI) technology. This trade-off can be compensated with accuracy and is vanquished by the development of Approximate Computing (AC). In this paper, six diverse Approximate Adders (AAs) have been proposed based on logic complexity reduction at the transistor level. Simulation results reveal that the Proposed AAs has a significant amount of Power and Delay savings, lesser Power-Delay Product (PDP). The Proposed AAs:PA1, PA3, PA5, PA3 exhibits 12.85 %, 41.59%, 72.05 %, 1.91% lesser power than the Existing AAs EAA1, EAA5, EAA6, EAA9 respectively. The Proposed AAs: PA2, PA3 incorporates 37.5 %, 54.5%, of lesser number of transistors compared to Existing AAs: EAA5, EAA9 whereas PA4, PA5 incorporates 40 % of reduction in the number of transistors compared to Existing AAs: EAA6, EAA8. These results are promising for high performance and energy efficient systems for error-resilient applications such as multimedia and signal processing where a slightly degraded output quality is acceptable, which could lead to significant power reduction.