A Critical Analysis of Approximate Adders: Correctness and Analysis of Performance

Abstract

In digital Very Large-Scale Integration (VLSI) the adder is a basic computational block for many circuits. Approximate adders were proposed as feasible solution in error-tolerant applications to provide a proper trade-off with accuracy to have better performance parameters in terms of energy, area, and delay. The state of the art of approximate adders are demonstrated in order to greatly enhance the operational features. To obtain the greatest number of approximation advantages, in this paper a systematic comparison between different approximate adders is presented. Highlighted Approximate Adder as a root map for various applications, which is more useful for some of the researcher's work in this field. This paper looks at existing estimated adder designs and compares them in terms including both error and circuit characteristics. Four different Approximate adders are reviewed in terms of Area, Delay, Simulation time and device utilization summary. Gate level implementation of selected adders are described in detail. The cost functions of selected Approximate adders are compared against various FPGA standard architectures. This paper looks at existing estimated adder designs and compares them in terms including both error and performance analysis. Comparison Results indicate an average of 49% change in Area Delay Product (ADP) and 6% variation in Simulation time.