Design of approximate adders and multipliers for error tolerant image processing

Abstract

An adder is the basic computational circuit in digital Very Large Scale Integration (VLSI) design. To improve the design metrics of an adder, Approximate Adders (AAs) have been proposed. These adders have been applied and analyzed on 8 × 8 Dadda multipliers (DMs). The design metrics of proposed AAs, Approximate Dadda Multipliers (ADMs) are synthesized in Cadence Register-Transfer Level (RTL) compiler and compares the design metrics with three different technology nodes. The quantitative characterization such as Error Distance (ED), Error Rate (ER), Pass Rate (PR), Mean Error Distance (MED), Normalised Error Distance (NED) of AAs, and ADMs are computed. Image blending and sharpening approaches have been applied using AAs, and approximate multipliers respectively to analyse the image quality metric using the proposed approximate framework.