Improved Retention Characteristics of Z2-FET Employing Half Back-Gate Control

Abstract

The structure of zero impact ionization, zero subthreshold swing field-effect transistor (Z2-FET) has been modified by stacking a half side of back-gate (BG) with a heavily doped silicon layer instead of full covered BG. Through the modification, the memory window and retention time are significantly improved. For the modified Z2-FET, the retention time of “0”-state increases from $800~\mu \text{s}$ to 800 ms by reducing the read voltage from 1.1 to 1.0 V compared to the conventional Z2-FET. The simulation results show that the half BG helps the potential barrier to sustain the “0”-state longer without the potential collapse. The modified devices have wider memory window and larger sense margin than the conventional Z2-FET with full covered BG.