(Invited) Special Memory Mechanisms in SOI Devices

Abstract

While the scaling of MOS transistors is still ongoing, the miniaturization of the DRAM storage capacitor is reaching a technology barrier. A promising solution consists of eliminating the capacitor. Instead, the charges can be stored in the floating body of an SOI MOSFET, which is also used to read out the memory states. Several floating-body 1T-DRAM variants with planar or multi-gate configuration have been proposed. We will show that 1T-DRAMs are also compatible with the ’unified memory’ paradigm: combining, within a single SOI transistor, volatile, nonvolatile and multiple-state memory functionalities. We will focus on our novel concepts, by addressing the device architecture, operating mechanisms, and scaling issues. MSDRAM – The device is based on the MSD hysteresis effect. The back channel is biased in moderate inversion and the front gate in strong accumulation such as to trigger B2BT that rapidly fills the body with holes (state ‘1’: high current). If B2BT is inhibited, there is no current flowing (state ‘0’). A wide memory window is obtained and the current ratio I1/I0exceeds 6 orders of magnitude. Specific source and drain architectures and ultrathin BOX allow enhancing the retention time while reducing the programming voltage, back-gate bias and power consumption. We present recent experiments in small-area MOSFETs that confirm the key assets of the MSDRAM. ARAM FAMILY – The ARAM concept consists in adding a middle oxide (MOX) in the body. The upper semi-body serves for hole storage and the lower semi-body for electron current sensing. To write ‘1’, excess holes are generated by impact ionization or B2BT in the upper semi-body. These holes induce a dynamic increase of the upper semi-body potential, which allows an electron current to flow in the lower semi-body via electrostatic coupling. If no holes are stored, the lower semi-body is fully depleted and no current flows (state '0'). The A2RAM has the body composed of a fully depleted P-layer on top of a thin N+layer, without MOX. Encouraging results have recently been obtained on thin and thick SOI structures. A(2)RAM principles are also applicable in DG MOSFETs and FinFETs. Z2-RAM – The Z2-FET is a forward-biased PIN diode, where the fully depleted body is only partially covered by the gate. At low drain voltage the diode is initially blocked because the front and back gates are biased to form potential barriers that prevent the injection of electrons and holes from the N and P contacts, respectively. This gate biasing emulates a PNPN thyristor configuration, but without any body doping. To program the ‘1’ or ‘0’ states, holes are stored or not under the negatively biased gate. Memory readout consists in discharging the stored charge that turns on the Z2-FET. In ‘0’ state, there is no discharge current and the diode remains blocked. UNIFIED MEMORY – The URAM combines non-volatile memory (NVM) and DRAM functionalities in a single transistor. A NVM charge trapping layer (ONO) is added to the 1T-DRAM structure. Electrons injected and trapped in the silicon nitride layer by Fowler Nordheim or hot carrier mechanisms, modify the MOSFET threshold voltage. Simultaneously, the floating body is used as a storage volume for the 1T-DRAM function. Our results demonstrate the feasibility of URAM in FinFETs with ONO BOX. In conclusion, the floating-body capacitorless DRAM is a very attractive memory device. There are several competing 1T-DRAM options among which the technologists and circuit designers will make the selection. B2BT is efficient for ‘1’ state programming, whereas capacitive coupling is suitable for ‘0’ state. 1T-DRAM volatile memory capability can be enriched by adding nonvolatile charge storage.