Abstract
In this paper an improved method to design a power optimized pipeline ADC is presented. By analyzing the architecture of SHA and the dependency of power on SNR, supply voltage and sampling rate, the flowchart instructing the design of pipeline ADC is put forward which simultaneously determines the resolution distribution, the optimum value for capacitors scaling factor, the parameter of OTA in each stage. A 0.18-mum 10-bit 80-MS/s CMOS prototype achieves 58.1 dB SNDR is implemented to validate the power scaling approach.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
