10.2 A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness

Abstract

A highly integrated wireline receiver with advanced modulation schemes desires multi-GS/s medium-resolution single-channel ADCs with a compact area for mass interleaving. Pipelined SAR ADCs have drawn a lot of attention for their great energy efficiency [1]; however, their conversion rate is still limited due to the serial conversion feature of the SAR quantizer. Benefiting from the highly digital structure with a decent area, time-domain (TD) pipelined ADCs [2] can be a promising alternative. While their competitiveness is reduced when sub-stage resolution is >4b, due to the exponentially increased power and area overhead in the TD flash architecture. To reach an overall 10b target, adding more stages together with high-performance inter-stage amplifiers is necessary, which often constrains the overall conversion rate. Such downside can be resolved by the post-amplification residue generation (PARG) technique in [3] that accelerates the pipeline operation by conducting the quantization and amplification in parallel. While this technique suffers from poor linearity due to the considerable swing in the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> stage, the ADC can hardly reach >6b resolution. To break the above bottlenecks among speed and resolution, while maintaining a comparable efficiency with the pipelined SAR ADC, this paper presents a time-assisted residue generation (TARG) technique, facilitating a 10b single-channel 2.6GS/s TD pipelined ADC. The TARG-based pipelined ADC facilitates a low-linearity time residue to considerably compress the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> stage residue transfer time, and simultaneously enables a high-linearity TD PARG, decoupling the tradeoff between linearity and speed of the time residue generation. Furthermore, the inherent complementation characteristic between V-T and T-V conversion in the TARG scheme makes the TD pipelined ADC intrinsically PVT robust without the gain calibration in [2]. Running at 2.6GS/s, the design experiences a 1.55dB SNDR drop under ±5 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">%</sup> supply variation and a 1.25dB SNDR loss across -40°C to 85°C.