Implementation of LPDDR4 Memory Interface Using AXI3 Protocol with Optimization Technique

Abstract

In electronics, one of the complex designs is SOC (system on chip) design, where many of the predefined or IP (intellectual property) circuits which can be analog, digital, or mixed-signal will be combined with each other and said that many circuits are combined to a single chip. In this paper, it is been designed the low power double data rate version of 4 memory (LPDDR4). It is one of the SDRAM architecture and since it is a memory there should be required a protocol to read data from memory and to write data from the memory for that purpose an AXI3 protocol is been used and the memory controller is been used to check the given input from the AXI protocol is correct or not. The entire SOC design is implemented using Verilog code and checked in the Xilinx 14.7 ISE and simulation is verified then the RTL is viewed in ModelSim 10.5 tool and verified the code coverage of design and testbench.