Abstract
The Scalable Parallel Random Number Generators (SPRNGs) library is widely used in computational science applications such as Monte Carlo simulations since SPRNG supports fast, parallel, and scalable random number generation with good statistical properties. In order to accelerate SPRNG, we develop a Hardware-Accelerated version of SPRNG (HASPRNG) on the Xilinx XC2VP50 Field Programmable Gate Arrays (FPGAs) in the Cray XD1 that produces identical results. HASPRNG includes the reconfigurable logic for FPGAs along with a programming interface which performs integer random number generation. To demonstrate HASPRNG for Reconfigurable Computing (RC) applications, we also develop a Monte Carlo π-estimator for the Cray XD1. The RC Monte Carlo π-estimator shows a 19.1× speedup over the 2.2 GHz AMD Opteron processor in the Cray XD1. In this paper we describe the FPGA implementation for HASPRNG and a π-estimator example application exploiting the fine-grained parallelism and mathematical properties of the SPRNG algorithm.
Highlights
Random numbers are required in a wide variety of applications such as circuit testing, system simulation, gameplaying, cryptography, evaluation of multiple integrals, and computational science Monte Carlo (MC) applications [1].In particular, MC applications require a huge quantity of high-quality random numbers in order to obtain a high-quality solution [2,3,4]
In order to provide the high-quality, scalable random number generation associated with SPRNG combined with the capabilities of High-Performance Reconfigurable Computing (HPRC), we developed the HardwareAccelerated Scalable Parallel Random Number Generators library (HASPRNGs) that provides bit-equivalent results to operate on a coprocessor Field Programmable Gate Arrays (FPGAs) [16,17,18]
Each Hardware-Accelerated version of SPRNG (HASPRNG) generator occupies a small portion of the FPGA, leaving plenty of room for Reconfigurable Computing (RC) MC candidate applications
Summary
Random numbers are required in a wide variety of applications such as circuit testing, system simulation, gameplaying, cryptography, evaluation of multiple integrals, and computational science Monte Carlo (MC) applications [1]. In order to provide the high-quality, scalable random number generation associated with SPRNG combined with the capabilities of HPRC, we developed the HardwareAccelerated Scalable Parallel Random Number Generators library (HASPRNGs) that provides bit-equivalent results to operate on a coprocessor FPGA [16,17,18]. The computational science application could be executed on the node microprocessors with the FPGAs accelerating the PPRNGs, the HASPRNG implementation could be colocated with the MC application on the FPGA. The latter approach avoids internal bandwidth constraints and enables more aggressive parallel processing. In this paper we describe the implementation of the HASPRNG library for the Cray XD1 for the full set of integer random number generators in SPRNG and demonstrate the potential of HASPRNG to accelerate RC MC applications by exploring a π-estimator on the Cray XD1
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