Impact of technology scaling on performance of domino logic in nano-scale CMOS

Abstract

With the scaling of the CMOS technology, domino logic circuits experience larger leakage currents, which affect their robustness and performance. The leakage can be compensated by using a properly sized PMOS keeper transistor, at the cost of circuit delay increase. Hence, it is expected that the performance improvement of domino logic will stop in future technology nodes, due to increased required keeper size to maintain robustness. In this paper, we will study different methods of keeper sizing for comparing the performance of CMOS-OR domino logic circuits designed using Predictive Technology models of 32nm, 22nm and 16nm CMOS technology nodes. The keeper size will be adjusted to obtain the same robustness (noise immunity) across the technology generations. With this method of keeper sizing across technology nodes, the simulation results shows that indeed the delay of a low fan-in domino circuit increases from 32nm to 22nm node and the domino circuits fail to operate at 16nm node. For a high fan-in domino gate, however, the delay reduces from 32nm to 22nm; and the circuit fails at 16nm.