Creating an affordable 22nm node using design-lithography co-optimization

Abstract

Achieving the required time-to-market with economically acceptable yield levels and maintaining them in volume production has become a daunting task for the advanced technology nodes. These difficulties are primarily attributable to the increase in process variability that is incurred while aggressively scaling technology nodes which are based on the same fundamental device architectures and process solutions. The introduction of a Metal Gate/High-K (MGHK) stack at the 32/28nm technology node will help in addressing the random variations due to random dopant fluctuations (RDF), but its benefit will be exhausted after a single process generation [3]. As a result, for the 22/20nm technology nodes, the only hope to limit RDF will be to adopt novel device architecture, such as FinFET and Ultra Thin Body or Fully Depleted SOI, that would reduce the dopant concentration in the channel. In addition to the RDF and other random effects, such as line edge roughness, etc., aggressive scaling has been increasing the layout dependent systematic variability largely due to resolution limitations and the application of stressors in modern device architectures [3]. It is important to recognize that if left unchecked, these systematic variations will have a prohibitive impact on the designs targeted towards 22nm technology nodes. Moreover, the inability to scale the wavelength of the light source used for lithography has led to a rapid increase of process and design costs. In particular, the lack of progress in extreme ultraviolet lithography (EUVL) will result in the need to define 22nm technology node using expensive double patterning technologies (DPT) for critical layers [1, 2]. As a result, complex DFM flows have been proposed as an attempt to model various printability and layout dependent effects; however, the increase in design flow complexities, lack of accuracy, and the tremendous expense of maintaining updated models required for these methods has marred their adoption. We believe a different approach is required to minimize the systematic variations that will plague the future technology nodes. Specifically, the industry should abolish the reactive DFM solutions and adopt a pro-active approach to DFM by increasing the level of abstraction and working towards a co-development of process and design. We propose a novel design methodology based on a set of fully pre-characterized circuit elements, or templates that will ensure a correct by construction integrated circuit design [2]. The methodology will permit the industry to take the next step in Moore's law with the application of smarter and more efficient circuit, layout, and lithography co-design techniques. In addition, we will examine the lithographic limitations that will be encountered in future technology nodes, including the 22nm node, and show how the proposed template-based design methodology can be used to overcome these challenges. The key enabler of the methodology is the creation of a regular design fabric onto which one can efficiently map the selected logic-templates using a limited number of printability-friendly layout patterns. The co-optimization of circuit, layout, and process (Figure 1) is achieved by selection of logic functions, circuit styles, layout patterns, and lithography solutions that jointly result in the lowest cost per good die. The resulting set of layout patterns and physical templates are then fully characterized on silicon through the use of specially designed test structures. By ensuring complete coverage, the proposed methodology is able to assure first pass silicon success. We will show how template-based design methodology can enable future technology nodes that can utilize current generation lithography while minimizing the cost per good die. In particular, we will: discuss the choices of regular design fabrics and their implications on design metrics, such as power, area, and performance, resulting yields, and overall cost; show that the selection of circuit topologies can be mapped efficiently to the choice of regular design fabric; and compare lithography solutions such as DPT, direct write multi-e-beam (MEBM), and interference lithography (IL) for the 22nm technology node and beyond.