Impact of Sacrificial Cosumption of Substrate By Thermal Oxidation on Electron Mobility of 4H-SiC Mosfets

Abstract

4H-SiC MOSFETs are extensively studied for high-voltage power device applications, however, the control of MOS interface properties have been one of the most challenging issues to meet the requirements of low on-resistivity and high-reliability. A significant degradation of electron mobility in inversion channel has been often reported, however, the dominant factors which deteriorate the channel characteristics have not yet been clarified well. In this study we investigated the effects of thermal oxidation during MOSFET fabrication processes on the quality of substrate surface, from the view point of channel mobility degradation. Lateral n-MOSFETs with various gate length, Lg=80~500 μm, were fabricated on p-type 4H-SiC (0001) wafers with Al-doped epitaxial layers. Source/drain (S/D) regions were formed by P implantation, followed by an activation annealing at 1650°C with a carbon cap. Ni Ohmic contacts for n+ S/D were formed by PMA at 1000°C for 1 min in N2 ambient. Finally Al was deposited and patterned as the gate electrode. Before the gate oxide formation, we intentionally consumed 5~60 nm of SiC substrate by a thermal oxidation followed by a chemical etching of SiO2 in HF solution. The gate oxide was thermally-grown in dry-O2 at 1300°C, followed by a post-oxidation-annealing in O2 at 800°C [1]. The consumed SiC thickness in total, including the gate oxide formation process as the final step, was varied from 9 to 72 nm. As a result, a degradation of field-effect-mobility was clearly observed when the sacrificially-consumed SiC thickness increased. To avoid the additional effects of surface damage due to the high-temperature activation annealing, we also prepared a MOSFET without 1650°C annealing, and successfully observed a further enhancement of channel mobility ~10% by minimizing the consumed SiC thickness during the device fabrication processes. Even though we expected the activation of only a few percentage of implanted P atoms, thanks to the thermal oxidation process at 1300oC for this sample, we could extract the channel mobility after the calibration of the effects of the parasitic resistance from Lg-dependence of channel resistance. These results clearly indicate that the sacrificial consumption of SiC substrate surface results in a monotonic degradation of channel mobility. The mechanism of such deterioration has not been clarified yet, but we believe that a degradation of SiC surface quality, possibly due to an accumulation of Al dopants [2] or interstitial C atoms near the SiC surface during the oxidation processes, would explain such change of MOSFET performance.[1] R. H. Kikuchi and Koji Kita, Appl. Phys. Lett. 105, 032106 (2014).[2] T. Kobayashi et al., Appl. Phys. Express 7, 121301 (2014).