Investigations on pre-oxidation nitrogen implantation for the improvement of channel mobility in 4H-SiC MOSFETs

Abstract

State-of-the-art 4H-SiC power MOSFETs are extremely attractive for modern power switching systems due to their superior performance and higher efficiency compared to conventional Si technology. The first generation commercial 4H-SiC DMOSFETs will have sufficient performance and reliability to address most of the current application areas but for more energy efficient future applications, further improvements are imperative. Historically, 4H-SiC MOSFETs have been plagued by high channel resistances due to an exceedingly low mobility of electrons in the inversion channel. The development of the NO post-oxidation annealing process has improved the channel mobility to an acceptable level but further improvement is highly desirable. Recently, implantation of N ions into SiC prior to oxidation has been suggested as an alternate method for improving the mobility of 4H-SiC MOSFETs [1]. This new process is attractive as it offers higher flexibility for accurately controlling the amount of N at the SiO 2 /SiC interface and also requires a substantially lower thermal budget. This process also raises intriguing questions regarding the mechanism by which N improves channel mobility. In this work, 4H-SiC MOS capacitors and lateral test MOSFETs fabricated using a similar N implant process have been investigated further and compared to typical NO annealed devices. The relevant N implantation into 4H-SiC was performed immediately prior to gate oxidation using 20 keV N+ ions through a ~600 A screen oxide. The ion dose into 4H-SiC was varied from 2.8×1013 cm-2 to 2.2 ×1014 cm-2. The room temperature field-effect mobilities of devices fabricated by using this process is shown in Fig. 1. The results show that ‘NO like’ mobility can be achieved even with the lowest dose employed, consistent with the results reported in [1]. From the transfer characteristics shown in Fig. 1, it is clear that increasing the N dose decreases the threshold voltage which becomes negative. This partially correlates to the significantly higher amount of positive fixed charge detected on n-MOS capacitors fabricated using the same methods (results not shown). Interface trap density (D it ) measurements using the conductance technique (Fig. 3) indicate these interfaces have a similar or lower density of ‘fast’ interface traps compared to NO annealed interfaces. However, from I–V hysteresis, the concentration of ‘border traps’ or 'slow, oxide traps in the near-interfacial oxide was estimated to be ~1×1012 cm-2 and ~5×1012 cm-2 for the lowest and highest N doses, respectively. This is more than an order of magnitude higher than the slow trapping observed in typical NO oxides. In this context, a new process in which pre-oxidation N implants have been used in conjunction with NO post-oxidation annealing (labeled NO+N in Fig. 4) has been directly compared to the ‘NO only’ case. As shown in Fig. 4, the additional pre-oxidation N implants leads to an impressive improvement of the mobility but also decreases the threshold voltage. Interestingly, the NO+N process is significantly superior with respect to reduced border trapping (results not shown), consistent with previous work on NO nitride oxides [2].