Abstract
Accelerated neutron tests for soft error rate (SER) are carried out using unbalanced feedback-loop circuits fabricated by Si and embedded SiGe (eSiGe) processes. The contribution of the p-type metal–oxide–semiconductor field effect transistor (PMOS) to total SER is shown to substantially decrease in the eSiGe process. The characteristics of parasitic bipolar transistors in PMOSs with and without eSiGe are investigated using technology computer-aided design (TCAD) simulations. We find that the narrow band gap of SiGe causes an increase in the rate of electron flow from the well region (Si) to the source region (SiGe), leading to a decrease in the current gain of the parasitic bipolar transistor in PMOS with eSiGe. Our results indicate that eSiGe can be attributed to the suppression of the parasitic bipolar effect, resulting in a reduced contribution of PMOS to SER.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.