III-V Quantum Well Field Effect Transistors on Silicon for Future High Performance and Low Power Logic Applications

Abstract

This work summarizes the advantages and challenges of III-V channel transistors for high performance and low power logic applications with respect to Si CMOS. The challenge of heterogeneous integration of III-V on Si is addressed by integration of In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> As QWFETs on Si substrates with a total composite buffer thickness successfully scaled down to 1.3um. The main advantages are demonstrated with Schottky-Gate In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> As QWFET on Si substrate showing 4.6X to 3.3X effective velocity gain over Si n-MOSFET for a VCC range of 0.5V to 1.0V, and 65% intrinsic drive current gain over Si nMOSFET at VCC = 0.5V. In addition, the challenge of further scaling and reduction of the high gate leakage that occurs in Schottky-gate devices is addressed by successful integration of an advanced composite high-K gate stack in the In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> As QWFET.