ICOACH: A circuit optimization aid for CMOS high-performance circuits

Abstract

iCOACH is a two-pass iterative circuit optimizer which generates a polycell-based layout from a gate level description file and user-defined timing constraints. The first pass is to generate, place and route the cells and extract the interconnection parameters. The second pass optimizes the circuit at the transistor level and makes necessary layout adjustments including pitch-matchings. Although iCOACH has the layout style similar to the polycell approach, it is distinct in two important aspects. First, iCOACH does not rely on any fixed cell library. Instead iCOACH generated customized cells by invoking the circuit optimizer and performs the transistor-level optimization for both static and dynamic CMOS circuits and their layouts under realistic constraints. Secondly, although the cells in the same row are required to have the same height, different rows can have different heights to make circuit more compact. Dynamic circuits are used with a careful treatment on reliability issues related to charge sharing and noise margin, which has not been treated rigorously in the previous literature. An area-efficient polycell layout style is also introduced for dynamic CMOS circuits. A 4-bit ALU and a 32-bit adder examples are presented to demonstrate the capability of iCOACH.