A CMOS design style for logic circuit hardening

Abstract

We present a novel CMOS design style that effectively reduces the impact of radiation-induced single event transients (SET) on logic circuits. This design style can be used in both static and dynamic CMOS circuits, and does not require any passive elements such as resistors or capacitors. A static circuit designed in the proposed style has two output ports while a dynamic circuit has one. This design style achieves SET mitigation by incorporating two techniques simultaneously: (1) transistors that are closest to the output terminals are placed in isolated wells and their body terminals tied to the corresponding source terminals - the resulting low electric fields across the drain-body and source-body junctions significantly weaken the charge collection efficiency; (2) SETs caused by charge collection near other transistors outside the isolated wells are attenuated via voltage division. Simulations show that in an inverter chain, one inverter stage is sufficient to attenuate the SET generated in the previous stage. This indicates that the soft error rate of a clock distribution network made of hardened inverters is only limited by the last stage, where the local clock signals are applied to sequential logic circuits or the dual outputs are converted to a single output. A hardened D-latch implemented in proposed design style is shown to have a critical charge value of at least 100 fC, as compared to the value of 7.5 fC for a conventional D-latch. Design examples of complex combinational static and dynamic circuits are also described and simulation results are presented.