ICOACH: a circuit optimization aid for CMOS high-performance circuits

Abstract

iCOACH is a two-pass iterative circuit optimizer which generates a polycell-based layout from a gate-level description file and user-defined timing constraints. The first pass is to place and route the cells and extract the interconnection parameters. The second pass optimizes the circuit at the transistor level and makes necessary pitch-matchings. Although iCOACH has a layout style similar to the polycell approach, it is distinct in two important aspects. First, iCOACH does not rely on any fixed cell library. Instead it generates customized cells by invoking the circuit optimizer and performs the transistor-level optimization for both static and dynamic CMOS circuits. Second, although the cells in the same row are required to have the same height, different rows can have different heights to make circuit more compact. Dynamic circuits are considered, with a careful treatment of reliability issues related to charge sharing and noise margin. A novel polycell layout style for dynamic CMOS circuits is introduced. A 4-bit ALU and a 32-bit adder are used to demonstrate the capability of iCOACH. >