Hole mobility in Strained Si/Relaxed SiGe/Si(110) hetero structures studied by gated Hall measurements

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Strained Si/relaxed SiGe/Si(110) heterostructures are gaining interest because the high hole mobility of them are suitable for realization of high-performance Si-wafer-based CMOS devices. Because the theoretical hole effective mass of the (110)-oriented tensile-strained Si is less than half of that of the unstrained Si. The strained Si layer thickness is one of the parameters that determine the device characteristics, because the strain and the crystalline quality of the strained Si layer depends on it. In this study, the samples with various strained Si layer thicknesses (20–136 nm) were grown on SiGe/Si(110) structures using the solid source molecular beam epitaxy (SSMBE) method. The electrical characteristics were evaluated by the gated Hall measurements in which the Hall measurements were performed with applying gate bias voltage. We confirmed that the mobility and the density of the carriers measured in the gated Hall measurements correspond to those of the holes driven by the gate bias voltage. The hole mobility is the highest for the sample with the 20 nm thick strained Si and decreases with increasing the strained Si layer thickness. This dependence of the hole mobility can be explained as results of the reduction of the lattice strain and the increase of the crystalline defects as the strained Si layer thickness increases.