A study of processed and unprocessed dual channel Si/SiGe MOSFET device structures using FIB and TEM

Abstract

We present the analysis of a series of Si/SiGe dual channel MOSFET device structures and their corresponding unprocessed blanket layers using transmission electron microscopy. These layers comprise a linear graded Si0.85Ge0.15 virtual substrate, followed by a compressively strained Si0.70Ge0.30 layer and capped with a tensile strained Si layer. It is found that high temperature metal oxide semiconductor processing induces Ge out-diffusion from the strained SiGe layer while the strained Si layer thickness was reduced by 50 % at the wafer edge due to cross wafer growth variations of the channel layers at low temperatures.