Brief overview of the impact of thermal stress on the reliability of through silicon via: Analysis, characterization, and enhancement

Abstract

Three-dimensional (3D) integration is considered an effective approach to extend and expand Moore's Law. Among them, Through-Silicon Via (TSV) technology provides mechanical support, heat conduction, and electrical connections for vertically stacked chips. The multilayer interface structure of TSV and the significant differences in the coefficient of thermal expansion (CTE) between layers can lead to complex thermal stress in TSV structures under heating conditions, which can degrade the performance of Three-Dimensional Integrated Circuits (3D ICs). This article systematically summarizes the current research status of copper pillar extrusion protrusions, Cu/Si interface integrity damage, and carrier mobility changes caused by thermal stress, focusing on the failure mechanisms and models of each aspect, elucidating the influencing factors and potential destructive failures. It then outlines and compares the advantages and disadvantages of micro-Raman spectroscopy, bending beam technology, and synchrotron X-ray microdiffraction technology in characterizing thermal stress in TSV structures. Characterizing thermal stress is beneficial for determining stress distribution and reliability risks of TSV. Finally, based on the analysis of the reliability impacts of the three major aspects mentioned above, measures to reduce the reliability impacts of thermal stress from the perspectives of heat dissipation, structure, materials, and processes in recent years are summarized. This article aims to deepen researchers' understanding of the main failure modes caused by thermal stress on TSV structures and provide theoretical guidance for building stable and reliable TSV structures.