Highly scaled (Lg ∼ 56 nm) gate-last Si tunnel field-effect transistors with ION > 100 μA/μm

Abstract

Planar band-to-band tunneling FETs (TFETs) have been fabricated on silicon-on-insulator (SOI) substrates using conventional CMOS technologies with a highly scaled sub-60nm gate length (effective gate length [Lg]∼40nm due to an overlap between the source and gate) and different anneal sequences. The optimal anneal sequence including spike and flash annealing resulted in a drive ON current (ION))>100μA/μm with ION/IOFF>105 at a drain bias of −1V. The devices exhibited negative differential resistance and non-linear subthreshold temperature dependencies, consistent with the band-to-band tunneling mechanism. Simulations using a 2-D TCAD simulator, MEDICI, agreed with experimental data, demonstrating the possibility of Si tunnel transistors in logic applications.