Impact of the gate structure on ESD characteristic of tunnel field-effect transistors

Abstract

Tunnel field-effect transistor (TFET) is a promising candidate in replacing a MOSFET, particularly for the next generation low-power integrated circuits (ICs). The gate grounded TFET (ggTFET) is considered as a basic electrostatic discharge (ESD) protection device in the TFET ICs. In this work, the impact of the gate structure on the ESD characteristic of the TFETs has been investigated using TCAD simulation. It is found that the technology parameters such as gate length, gate oxide thickness, and gate structure geometry affect both the triggering voltage and the failure current of the TFET.