High-brightness LEDs of big chip size on multi-layer interconnects with optimized thermal dissipation and optical performance

Abstract

The market share of high-brightness LEDs in general lighting has been rapidly expanding mainly owing to the continued technological advances on internal quantum efficiency, light extraction and wavelength conversion. In spite of these promising advances, there remain some key breakthroughs to be made before LED lighting technology can be fully adopted into the broad market, with emphasis on efficient thermal dissipation, higher efficacy at high brightness, and low manufacturing cost. Higher brightness requires LEDs to be operated at higher current density which results in efficacy degradation due to droop behavior and thus higher power loss into heat and shorter lifetime. Therefore a highly efficient mechanism of thermal dissipation is needed for timely conduction of heat away from the high-power LED chip. For general lighting at high brightness, a large chip size is preferable. More importantly, with larger chip size, higher brightness can be achieved at much lower current density which leads to less degradation of efficacy. However simply increasing the die size of LEDs in wafer fabrication causes significant yield loss and thus hinders the adoption of big-chip LEDs. In this paper we propose a scalable approach to enable larger chip sizes for manufacturing high efficacy & high brightness LEDs at high yield and low cost. The metric of lower cost per lumen is necessary for LEDs to be competitive to traditional light sources like fluorescent lights in the consumer market segment. About 50% of the total LED production cost is consumed by the packaging processes after the emissive device stack being fabricated. Also given the minimal thickness of the device stack, the key bottleneck for thermal dissipation resides in the packaging structure and its interface to the device stack. We address these two key challenges with a novel wafer-level packaging structure of metal contacts forming a perimeter that is integrated into the device stack, which optimizes the thermal dissipation rate from the active device stack to substrate while allowing high aperture ratio and improved light output. Our approach applies a wafer-level batch process starting from LED fabrication to packaging for internal and external light extraction as well as wavelength conversion, in order to achieve high throughput and high yield in a scalable and inexpensive manner. To improve the overall power efficiency, different materials have been selected for ohmic contacts and high reflectivity at p and n electrodes, and further developments continue to be implemented, including a current-spreading layer, large-area light extraction structure and integrated phosphor material. Flip chip packaging is chosen due to its advantage of full front-side emission, maximized aperture ratio, compact form factor, higher integration density and ease of wafer level processing. The substrates for flip chip packaging of LED chips are made of Si which was selected due to its relatively high thermal conductivity (149 W/m/K) and ease of fabrication with standard semiconductor processes. Multi-layer interconnects are patterned over the Si substrate with solder bumps built over the passivation openings for flip-chip assembly of multiple LED dies. The multi-layer dielectric stack of the substrate is designed to form dielectric mirror maximizing the reflection of emitted light back into the LED side for improved light output.