High-Resolution Delay Testing of Interconnect Paths in Field-Programmable Gate Arrays

Abstract

We present a new method of performing high-resolution path delay testing on designs targeted to field-programmable gate arrays. Our built-in self-test (BIST) architecture uses an on-chip delay line element to set the launch time of each test pattern generator to its optimum point for stressing paths in the routed chip. The rising and falling edges of each test pattern are controllable with high precision, and consequently, our test architecture catches very small timing faults that exist in the path. For example, on Xilinx Virtex-4, we catch defects as small as 78 ps using the IDELAY delay line circuit that is available on that device. Our approach was validated on Virtex-4, and the same method can be applied to any device that supports on-chip delay lines that are adjustable at runtime. Furthermore, our architecture simultaneously tests multiple paths to reduce the overall test time.