Abstract
We present a new method of performing high-resolution path delay testing on designs targeted to Xilinx Virtex-4 field-programmable gate arrays (FPGAs). Our built-in self-test architecture uses an on-chip delay line to set the launch time of test pattern generators to their optimum point for stressing paths in the chip. Consequently, it catches delay defects as small as 78 ps and tests multiple paths in parallel. Our approach was validated on Virtex-4 devices and the same method can be applied to other FPGAs that contain delay lines.
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