Abstract
For semiconductor devices, the use of amorphous carbon films as a sacrificial hard mask material is commonplace in the integration for patterning of 90 nm and below technology node devices. These films have an intrinsically low friction coefficient. At the same time, for planarity reasons, double‐side polished (DSP) wafers have been progressively introduced. The combination of double side polished silicon wafers, together with their covering with amorphous carbon film, dramatically decreases the friction coefficient and incommodes their robotic handling. This issue may be faced by developing a tool designed for that specific purpose, and by optimizing the deposition conditions so as to obtain a reliable industrial high‐yield process.
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