Generation of tests for the localization of single gate design errors in combinational circuits using the stuck-at fault model

Abstract

We propose a new approach to generate diagnostic tests and localize single gate design errors in combinational circuits. The method is based on using the stuck-at fault model with subsequent translation of the diagnosis into the design error area. This allows to exploit standard gate-level ATPGs for verification and design error diagnosis purposes. A powerful hierarchical approach is proposed for generating test patterns, which, at first, localize the faulty macro (tree-like subcircuit), and then localize the erroneous gate in the faulty macro. Experimental data show the efficiency of the macro-level test generation and fault simulation compared to the plain gate-level approaches.