A diagnosis method for single logic design errors in gate‐level combinational circuits

Abstract

This paper proposes a method for diagnosing logic design errors in gate-level combinational circuits, and discusses how to correct them. Some previously proposed design error models are explained at gate-level. This diagnosis method includes the vector pair analysis that has been developed for test pattern generation and fault diagnosis for multiple stuck-at faults. In vector pair analysis, logic values due to design errors are regarded as logic values caused by stuck-at faults and its results give some information on how to correct the design errors. However, since diagnosis using vector pair analysis cannot be applied to missing lines, their diagnosis uses another method based on the analysis of controlling values for input vectors with incorrect output responses. We also propose another diagnosis method for locating design errors in smaller areas, by the vector pair analysis. The experimental results for ISCAS'85 benchmark circuits show that the proposed method is effective for single design errors. © 1997 Scripta Technica, Inc. Syst Comp Jpn, 28(6): 30–39, 1997