Design error localization in digital circuits by stuck-at fault test patterns

Abstract

A brief description of basic concepts and the algorithm for a new hierarchical approach to the single gate-level design error diagnosis for combinational circuits based on the stuck-at fault model is presented. The localizing procedure starts at the higher signal path level where decision diagrams (BDD) are used for representing and localizing stuck-at faults. On the basis of detected faulty signal paths, suspected stuck-at faults at gate inputs are calculated, and then mapped into suspected design error(s). Experimental data on well-known benchmark circuits show the advantage of the proposed method compared to the known algorithms of design error diagnosis.