Gate stack insulator breakdown when the interface layer thickness is scaled toward zero

Abstract

To fully profit from the advantages of high-K materials in metal-oxide-semiconductor gate insulator stacks, the reduction in the silicon oxide interfacial layer thickness is being pursued. In the framework of the percolation model, we explore the effects of reducing the interfacial layer thickness on the dielectric breakdown of the gate stack. If the reduction in interface layer thickness is performed at constant equivalent oxide thickness, a significant improvement of oxide lifetime is predicted. Our results also suggest that it is possible to scale the equivalent oxide thickness without degrading the breakdown-related reliability.